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memory: make buffers aligned to CACHE_LINE_SIZE - #1568
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Please use PLATFORM_DCACHE_ALIGN.
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@tlauda currently not possible, we cannot include sof/platform.h to linker and the value of PLATFORM_DCACHE_ALIGN can be "sizeof(uint32_t)" which will not work in linker.
If we want to use it then we need to move it to another file and remove sizeof possibility
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This is platform specific linker script, not a universal one, so I'm fine with some HEAP_BUF_ALIGNMENT define in some common cAVS header file included by the linker script and also in another place followed by some C_ASSERT(0 == (HEAP_BUF_ALIGNMENT % PLATFORM_DCACHE_ALIGN)).
This value will determine alignment for heap buffers Signed-off-by: Adrian Bonislawski <adrian.bonislawski@linux.intel.com>
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lgirdwood
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commit message and please comment what this check does in the code.
This will check if heap buffers alignment is valid Signed-off-by: Adrian Bonislawski <adrian.bonislawski@linux.intel.com>
It provides better memory/cache performance since it aligns with memory IO burst size and cache line size Signed-off-by: Adrian Bonislawski <adrian.bonislawski@linux.intel.com>
It provides better memory/cache performance since it aligns with memory IO burst size and cache line size Signed-off-by: Adrian Bonislawski <adrian.bonislawski@linux.intel.com>
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done |
It provides better memory/cache performance since it aligns with memory IO burst size and cache line size Signed-off-by: Adrian Bonislawski <adrian.bonislawski@linux.intel.com>
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No changes, just force-pushed to trigger travis again |
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@lgirdwood please finish review. We need it for #1557 which is needed for #1567 :) |
As adviced in PR #1557 it provides better memory/cache performance since it aligns with memory IO burst size and cache line size
This PR will use CACHE_LINE_SIZE in CNL, ICL and SUE