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platform: amd: acp_7_x: re-enable S5 refclk for the DSP external timer #11405

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Merged
lgirdwood merged 1 commit into from
Nov 6, 2026
Merged

platform: amd: acp_7_x: re-enable S5 refclk for the DSP external timer #11405

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2 changes: 1 addition & 1 deletion src/platform/amd/acp_7_x/lib/clk.c
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Original file line number Diff line number Diff line change
Expand Up @@ -424,7 +424,7 @@ void acp_clk_d0_sequence(uint32_t clock_freq)
/* Run ACP off the undivided ACLK enable acp_clkmux_sel(ACP_CLK_DIV_BY_1);*/
/* Only now program the DFS divider: the slice is off bypass */
change_clock_notify(clock_freq);
/* S5_REFCLK back on the 24 MHz reference with the postdiv reset to enable it acp_s5_refclk_config(0, ACP_CLK_BYPASS_SEL_REFCLK_24MHZ, 0);*/
acp_s5_refclk_config(0, ACP_CLK_BYPASS_SEL_REFCLK_24MHZ, 0);
/* restore io clk acp_io_clk_sel_restore();*/
}

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