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platform: amd: acp_7_x: re-enable S5 refclk for the DSP external timer - #11405
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The Zephyr AMD_ACP_TIMER driver uses the ACP DSP0 External Timer1 as the system tick. This timer counts on S5_REFCLK, which must run at the 24 MHz reference rate. Restore the commented-out acp_s5_refclk_config() call in acp_clk_d0_sequence() so S5_REFCLK is put back on the 24 MHz reference after the DFS divider is programmed. Signed-off-by: Jyothikala P <Jyothikala.P@amd.com>
jyothikalap
requested review from
bhiregoudar and
sunilkumardommati
as code owners
November 5, 2026 10:29
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Can one of the admins verify this patch?
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lgirdwood
approved these changes
Nov 5, 2026
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@thesofproject/amd pls review. |
bhiregoudar
approved these changes
Nov 6, 2026
abonislawski
approved these changes
Nov 6, 2026
PR 11405: test resultsRun date: 2026-11-06 10:33 UTC Tested commit: 0764fb1d459e6c0c14466ac9e4bae6417f9c4123
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The Zephyr AMD_ACP_TIMER driver uses the ACP DSP0 External Timer1 as the system tick. This timer counts on S5_REFCLK, which must run at the 24 MHz reference rate.
Restore the commented-out acp_s5_refclk_config() call in acp_clk_d0_sequence() so S5_REFCLK is put back on the 24 MHz reference after the DFS divider is programmed.