rram

A Simulation Framework for Memristive Deep Learning Systems

This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of Dimitris Antoniadis (PG Taught Student) at Imperial College London

A well-posed RRAM SPICE model implemented in Verilog-A, based on Stanford/ASU filamentary model, using code developed at UC Berkeley

Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations

Series of ReRAM characterization modules compatible with Keithley Semiconductor Characterization Systemsinstruments

Code and repository for RRAM RADAR programming method: https://doi.org/10.1109/TED.2021.3097975

Memristor model: Various implementations of the simplified memristor model "JART-TUD VCM"

Memristive NODE

Crossbar Parasitics Simulator – A tool for benchmarking parasitic resistance models in RRAM crossbars and evaluating neural networks under realistic hardware constraints.

[Nature Communications 2025] "Random resistive memory-based extreme point learning machine for unified visual processing."

Long Short-Term Memory Implementation Exploiting Passive RRAM Crossbar Array

AI-agent skill, verified Python toolkit and executed six-chapter book on compact memristor models (linear ion drift, Yakopcic, VTEAM, Stanford-PKU), cross-checked against the MemrisTec Model Library

A free, picture-first beginner guide to memristors and ReRAM, with interactive experiments and an LTspice model.

Research-grade framework for memristive crossbar security analysis, fault injection, side-channel attacks, and PUF-based hardware defenses using MemTorch + PyTorch.

Scripts to model functional experimental or other phenomena, such as neuronal/device spiking, or tip-sample interactions.

Unified Open-Source FPGA Toolchain on WSL

PicoRV32 RISC-V SoC with behavioral RRAM memory, custom PCPI extensions, and UVM verification

NI RRAM programming in Python

A 74-page technical research report on the DEF CON 34 attendee badge and the Baochip-1x mostly-open 22 nm RISC-V SoC. Every claim graded Confirmed / Strong inference / Unknown.

RRAM resistive switching behavior evaluation and prediction, based on fabrication conditions. Applied Machine learning\Deep learning models to predict SET voltage distribution in Honey-based RRAM devices. Simulating the basic operations of RRAM crossbars in image classification tasks, investigating the robustness of in situ vs. ex situ training.