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dmic: don't decrement active FIFO count below 0 - #4159
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In case of a spurious DMIC interrupt flood the active FIFO count will decrement below 0. Prevent it by checking the current DAI state. Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
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Could it be possible that the hardware doesn't like getting too many stops? |
paulstelian97
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May 10, 2021
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The common HW resources for producing output FIFOs A and B are set up when active fifos == 0. If it went negative the initialization was skipped and data pushed to FIFOs is likely at rate that is not matching timer based scheduling and cause those overrun IRQs. |
singalsu
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May 10, 2021
singalsu
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singalsu
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Looks correct to me. Thanks!
jgunn0262
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May 10, 2021
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In case of a spurious DMIC interrupt flood the active FIFO count will decrement below 0. Prevent it by checking the current DAI state.
As a matter of fact this seems to also actually fix the spurious IRQ flood from the DMIC, although the reason is unclear.