schedule: implement dma_single_chan_domain

src/audio/dai.c

@@ -227,6 +227,7 @@ static int dai_playback_params(struct comp_dev *dev, uint32_t period_bytes)
 	config->dest_dev = dai_get_handshake(dd->dai, dev->params.direction,
 					     dd->stream_id);
 	config->is_scheduling_source = comp_is_scheduling_source(dev);
+	config->period = dev->pipeline->ipc_pipe.period;
 
 	trace_dai_with_ids(dev, "dai_playback_params() "
 			   "dest_dev = %d stream_id = %d "
@@ -293,6 +294,7 @@ static int dai_capture_params(struct comp_dev *dev, uint32_t period_bytes)
 	config->src_dev = dai_get_handshake(dd->dai, dev->params.direction,
 					    dd->stream_id);
 	config->is_scheduling_source = comp_is_scheduling_source(dev);
+	config->period = dev->pipeline->ipc_pipe.period;
 
 	/* TODO: Make this code platform-specific or move it driver callback */
 	if (dai_get_info(dd->dai, DAI_INFO_TYPE) == SOF_DAI_INTEL_DMIC) {

src/audio/host.c

@@ -626,6 +626,7 @@ static int host_params(struct comp_dev *dev)
 	config->cyclic = 0;
 	config->irq_disabled = pipeline_is_timer_driven(dev->pipeline);
 	config->is_scheduling_source = comp_is_scheduling_source(dev);
+	config->period = dev->pipeline->ipc_pipe.period;
 
 	host_elements_reset(dev);
 

src/audio/pipeline.c

@@ -669,7 +669,6 @@ int pipeline_trigger(struct pipeline *p, struct comp_dev *host, int cmd)
 {
 	struct pipeline_data data;
 	int ret;
-	uint32_t flags;
 
 	trace_pipe_with_ids(p, "pipeline_trigger()");
 
@@ -692,16 +691,13 @@ int pipeline_trigger(struct pipeline *p, struct comp_dev *host, int cmd)
 	data.start = host;
 	data.cmd = cmd;
 
-	irq_local_disable(flags);
-
 	ret = pipeline_comp_trigger(host, &data, host->params.direction);
 	if (ret < 0) {
 		trace_ipc_error("pipeline_trigger() error: ret = %d, host->"
 				"comp.id = %u, cmd = %d", ret, host->comp.id,
 				cmd);
 	}
 
-	irq_local_enable(flags);
 	return ret;
 }
 
@@ -823,7 +819,7 @@ static int pipeline_copy(struct pipeline *p)
 		start = p->sink_comp;
 
 		/* if not pipeline preload then copy sink comp first */
-		if (!p->preload) {
+		if (!p->preload && comp_is_active(start)) {
 			ret = comp_copy(start);
 			if (ret < 0) {
 				trace_pipe_error("pipeline_copy() error: "

src/drivers/dw/dma.c

@@ -462,6 +462,7 @@ static int dw_dma_set_config(struct dma_chan_data *channel,
 	/* default channel config */
 	channel->direction = config->direction;
 	channel->is_scheduling_source = config->is_scheduling_source;
+	channel->period = config->period;
 	dw_chan->cfg_lo = DW_CFG_LOW_DEF;
 	dw_chan->cfg_hi = DW_CFG_HIGH_DEF;
 

src/drivers/intel/cavs/hda-dma.c

@@ -606,6 +606,7 @@ static int hda_dma_set_config(struct dma_chan_data *channel,
 	channel->direction = config->direction;
 	channel->desc_count = config->elem_array.count;
 	channel->is_scheduling_source = config->is_scheduling_source;
+	channel->period = config->period;
 
 	/* validate - HDA only supports continuous elems of same size  */
 	for (i = 0; i < config->elem_array.count; i++) {

src/include/sof/lib/dma.h

@@ -127,6 +127,7 @@ struct dma_sg_config {
 	uint32_t src_dev;
 	uint32_t dest_dev;
 	uint32_t cyclic;			/* circular buffer */
+	uint64_t period;
 	struct dma_sg_elem_array elem_array;	/* array of dma_sg elems */
 	bool scatter;
 	bool irq_disabled;
@@ -210,6 +211,7 @@ struct dma_chan_data {
 	uint32_t desc_count;
 	uint32_t index;
 	uint32_t core;
+	uint64_t period;	/* DMA channel's transfer period */
 	/* true if this DMA channel is the scheduling source */
 	bool is_scheduling_source;
 

src/include/sof/lib/notifier.h

@@ -22,6 +22,7 @@ enum notify_id {
 	NOTIFIER_ID_CPU_FREQ = 0,
 	NOTIFIER_ID_SSP_FREQ,
 	NOTIFIER_ID_KPB_CLIENT_EVT,
+	NOTIFIER_ID_DMA_DOMAIN_CHANGE,
 };
 
 struct notify {

src/include/sof/schedule/ll_schedule_domain.h

@@ -131,4 +131,8 @@ struct ll_schedule_domain *dma_multi_chan_domain_init(struct dma *dma_array,
 						      uint32_t num_dma, int clk,
 						      bool aggregated_irq);
 
+struct ll_schedule_domain *dma_single_chan_domain_init(struct dma *dma_array,
+						       uint32_t num_dma,
+						       int clk);
+
 #endif /* __SOF_SCHEDULE_LL_SCHEDULE_DOMAIN_H__ */

src/platform/intel/cavs/platform.c

@@ -386,13 +386,12 @@ int platform_init(struct sof *sof)
 				  PLATFORM_LL_DEFAULT_TIMEOUT);
 	scheduler_init_ll(platform_timer_domain);
 
-	/* init low latency multi channel DW-DMA domain and scheduler */
+	/* init low latency single channel DW-DMA domain and scheduler */
 	platform_dma_domain =
-		dma_multi_chan_domain_init(
-				&dma[PLATFORM_DW_DMA_INDEX],
-				PLATFORM_NUM_DW_DMACS,
-				PLATFORM_DEFAULT_CLOCK,
-				IS_ENABLED(CONFIG_DW_DMA_AGGREGATED_IRQ));
+		dma_single_chan_domain_init
+			(&dma[PLATFORM_DW_DMA_INDEX],
+			 PLATFORM_NUM_DW_DMACS,
+			 PLATFORM_DEFAULT_CLOCK);
 	scheduler_init_ll(platform_dma_domain);
 
 	/* init the system agent */

src/schedule/CMakeLists.txt

@@ -2,6 +2,7 @@
 
 add_local_sources(sof
 	dma_multi_chan_domain.c
+	dma_single_chan_domain.c
 	edf_schedule.c
 	ll_schedule.c
 	schedule.c