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xtensa: add support for platforms with no threadptr register. - #1826
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I think we should update the whole header.
There is a high probability, that the rest of the values is also wrong.
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I checked the others and they looked correct.
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@tlauda in fact a few other items were off, now fixed. I will test over the weekend and see if it improves things.
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@lgirdwood Hard to tell from the code what can be wrong. If your macro loads the right address for the virtual threadptr, then it should work correctly. |
Yeah, validated on qemu. My suspicion is that level 1 IRQs are not used anywhere except on HSW/BDW since they have a different xtos entry compared to mid-high level IRQs (2 - 7). |
BYT/CHT uses level 1 as |
I see in CI that HSW fails and BDW boots OK. Is this expected, or maybe the exception you're seeing is not on BDW? Expected. Qemu has the wrong ISA config. |
Fix the core-isa headers for HSW and BDW. Provide a virtual threadptr register in the memory map using a linker area below the stack. This can then be referenced instead of the register for ISAs that dont support threadptr. This patch also includes initial vthreadptr support for HSW/BDW platforms. Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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@tlauda updated core-isa.h fixes the issue. FW can now boot again on BDW and perform IPC. Now need to update kernel and topology for XPS13. Good to merge. |
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@lgirdwood What with the HSW boot fail? I think we should first update QEMU in CI to avoid constant failures. |
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@xiulipan Travis will need an Qemu update now that thesofproject/qemu#19 is merged. This fixes all HSW/BDW issues. |
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@lgirdwood Let me have a try with the latest qemu. I think I hold the update for some issue with qemu and need to fix them all before make the update. |
| { | ||
| vector_reset_text : | ||
| org = XCHAL_RESET_VECTOR0_PADDR, | ||
| org = XCHAL_RESET_VECTOR_PADDR, |
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What is the reason of this change?
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change in core-isa.h, VECTOR0 no longer exists.
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SOFCI TEST |
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@xiulipan all qemu fixes now merged (including HSW/BDW ISA updates). |
Provide a virtual threadptr register in the memory map using a linker
area below the stack. This can then be referenced instead of the register
for ISAs that dont support threadptr.
This patch also includes initial support for HSW/BDW platforms.
TODO: This patch now allow BDW to boot on real HW and updated qemu, but it fails on any context switch to IRQ level1 ? i.e. scheduling IRQs seem to work but any IPC (level1) will process and then break next scheduler IRQ invocation (causing a kernel exception). @tlauda any ideas ?
Signed-off-by: Liam Girdwood liam.r.girdwood@linux.intel.com