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Merged
jajanusz merged 7 commits into from
Jun 11, 2019
Merged

memory: new memory layout #1483

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dbcd1b4
memory: use linker stack position in boot entry
abonislawski May 21, 2019
bfa08ad
linker: fix for symbol overwrite in byt linker
abonislawski Jun 3, 2019
7d4a84f
linker: fix for symbol overwrite in hsw linker
abonislawski Jun 3, 2019
a1b8d2d
linker: fix for symbol overwrite in imx8 linker
abonislawski Jun 10, 2019
420c98a
alloc: use linker heap position in sanity check
abonislawski May 28, 2019
66be406
stack: new macro to setup stack per core
abonislawski May 28, 2019
ecbe619
memory: new memory layout for APL, ICL, CNL and SUE
abonislawski May 28, 2019
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2 changes: 1 addition & 1 deletion src/arch/xtensa/boot_entry.S
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Expand Up @@ -43,7 +43,7 @@ l2_cache_pref:
#endif

sof_stack_base:
.word SOF_STACK_BASE
.word __stack

#if !defined CONFIG_SUECREEK
wnd0_base:
Expand Down
2 changes: 1 addition & 1 deletion src/arch/xtensa/smp/xtos/crt1-boards.S
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Expand Up @@ -231,7 +231,7 @@ xtos_per_core_init_interrupt_mask:

// Assign stack ptr before PS is initialized to avoid any debugger
// side effects and prevent from double exception.
xtos_stack_addr_percore_basic sp, a3, _stack_sentry, ARCH_STACK_SIZE
xtos_stack_addr_percore sp, a3, _stack_sentry, _sof_core_s_start, SOF_STACK_SIZE

/*
* Now that sp (a1) is set, we can set PS as per the application
Expand Down
23 changes: 23 additions & 0 deletions src/arch/xtensa/smp/xtos/xtos-internal.h
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Expand Up @@ -2,6 +2,7 @@
* xtos-internal.h -- internal definitions for single-threaded run-time
*
* Copyright (c) 2003-2010 Tensilica Inc.
* Copyright (c) 2019 Intel Corporation. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
Expand Down Expand Up @@ -31,6 +32,7 @@
#include <xtensa/xtruntime-frames.h>
#include <xtensa/xtensa-versions.h>
#include <platform/platform.h>
#include <platform/memory.h>
#ifndef XTOS_PARAMS_H /* this to allow indirect inclusion of this header from the outside */
#include "xtos-params.h"
#endif
Expand Down Expand Up @@ -333,6 +335,27 @@ XTOS_PENDING_OFS: .space 4 /* _xtos_pending variable */
add \ax, \ax, \ay
.endm

// xtos_stack_addr_percore ax, ay, stack_master, stack_slave, stack_size
// Retrieves address of end of stack buffer for certain core to register ax.
.macro xtos_stack_addr_percore ax, ay, stack_master_addr, mem_blk_slave_addr, stack_size
get_prid \ax
bnei \ax, PLATFORM_MASTER_CORE_ID, core_s
movi \ax, \stack_master_addr
j exit
core_s:
addi \ax, \ax, -1
movi \ay, _core_s_size
mull \ax, \ax, \ay
movi \ay, (HEAP_SYSTEM_S_SIZE + HEAP_SYS_RUNTIME_S_SIZE)
add \ax, \ax, \ay
movi \ay, \mem_blk_slave_addr
add \ax, \ax, \ay
j exit
exit:
movi \ay, \stack_size
add \ax, \ax, \ay
.endm

// xtos_stack_addr_percore_add ax, stack_name, offset
// Pointer to dedicated interrupt stack + offset.
.macro xtos_stack_addr_percore_add ax, stack_name, offset
Expand Down
4 changes: 3 additions & 1 deletion src/lib/alloc.c
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Expand Up @@ -798,8 +798,10 @@ void heap_trace(struct mm_heap *heap, int size) { }
/* initialise map */
void init_heap(struct sof *sof)
{
extern uintptr_t _system_heap_start;

/* sanity check for malformed images or loader issues */
if (memmap.system[0].heap != HEAP_SYSTEM_0_BASE)
if (memmap.system[0].heap != (uintptr_t)&_system_heap_start)
panic(SOF_IPC_PANIC_MEM);

spinlock_init(&memmap.lock);
Expand Down
113 changes: 43 additions & 70 deletions src/platform/apollolake/apollolake.x.in
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Expand Up @@ -90,21 +90,6 @@ MEMORY
sof_fw :
org = SOF_FW_BASE,
len = SOF_FW_MAX_SIZE
system_heap :
org = HEAP_SYSTEM_0_BASE,
len = HEAP_SYSTEM_T_SIZE
system_runtime_heap :
org = HEAP_SYS_RUNTIME_0_BASE,
len = HEAP_SYS_RUNTIME_T_SIZE
runtime_heap :
org = HEAP_RUNTIME_BASE,
len = HEAP_RUNTIME_SIZE
buffer_heap :
org = HEAP_BUFFER_BASE,
len = HEAP_BUFFER_SIZE
sof_stack :
org = SOF_STACK_END,
len = SOF_STACK_BASE - SOF_STACK_END
buffer_hp_heap :
org = HEAP_HP_BUFFER_BASE,
len = HEAP_HP_BUFFER_SIZE
Expand Down Expand Up @@ -152,11 +137,6 @@ PHDRS
vector_double_lit_phdr PT_LOAD;
vector_double_text_phdr PT_LOAD;
sof_fw_phdr PT_LOAD;
system_heap_phdr PT_LOAD;
system_runtime_heap_phdr PT_LOAD;
runtime_heap_phdr PT_LOAD;
buffer_heap_phdr PT_LOAD;
sof_stack_phdr PT_LOAD;
buffer_hp_heap_phdr PT_LOAD;
wnd0_phdr PT_LOAD;
wnd1_phdr PT_LOAD;
Expand Down Expand Up @@ -495,28 +475,61 @@ SECTIONS
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN (8);

. = ALIGN (SRAM_BANK_SIZE);
_runtime_heap_start = ABSOLUTE(.);
. = . + HEAP_RUNTIME_SIZE;
_runtime_heap_end = ABSOLUTE(.);

. = ALIGN (32);
_buffer_heap_start = ABSOLUTE(.);
. = . + HEAP_BUFFER_SIZE;
_buffer_heap_end = ABSOLUTE(.);

. = ALIGN (SRAM_BANK_SIZE);
_system_heap_start = ABSOLUTE(.);
. = . + HEAP_SYSTEM_M_SIZE;
_system_heap_end = ABSOLUTE(.);

. = ALIGN (32);
_system_runtime_heap_start = ABSOLUTE(.);
. = . + HEAP_SYS_RUNTIME_M_SIZE;
_system_runtime_heap_end = ABSOLUTE(.);

. = ALIGN (4096);
_sof_stack_start = ABSOLUTE(.);
. = . + SOF_STACK_SIZE;
_sof_stack_end = ABSOLUTE(.);

. = ALIGN (SRAM_BANK_SIZE);
_sof_core_s_start = ABSOLUTE(.);
. = . + SOF_CORE_S_T_SIZE;
_sof_core_s_end = ABSOLUTE(.);

_bss_end = ABSOLUTE(.);
} >sof_fw :sof_fw_phdr

/* stack */
_end = SOF_STACK_END;
PROVIDE(end = SOF_STACK_END);
_stack_sentry = SOF_STACK_END;
__stack = SOF_STACK_BASE;
_end = _sof_stack_start;
PROVIDE(end = _sof_stack_start);
_stack_sentry = _sof_stack_start;
__stack = _sof_stack_end;

/* Slave core size */
_core_s_size = SOF_CORE_S_SIZE;

/* System Heap */
_system_heap = HEAP_SYSTEM_0_BASE;
_system_heap = _system_heap_start;

/* system runtime heap */
_system_runtime_heap = HEAP_SYS_RUNTIME_0_BASE;
_system_runtime_heap = _system_runtime_heap_start;

/* module heap */
_module_heap = HEAP_RUNTIME_BASE;
_module_heap = _runtime_heap_start;

/* buffer heap */
_buffer_heap = HEAP_BUFFER_BASE;
_buffer_heap_end = _stack_sentry;
_buffer_heap = _buffer_heap_start;
_buffer_heap_end = _buffer_heap_end;

.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
Expand Down Expand Up @@ -569,46 +582,6 @@ SECTIONS
KEEP (*(.gnu.linkonce.xt.profile_files.*))
}

.system_heap (NOLOAD) : ALIGN(8)
{
. = ALIGN (32);
_system_heap_start = ABSOLUTE(.);
. = . + HEAP_SYSTEM_T_SIZE;
_system_heap_end = ABSOLUTE(.);
} >system_heap :system_heap_phdr

.system_runtime_heap (NOLOAD) : ALIGN(8)
{
. = ALIGN (32);
_system_runtime_heap_start = ABSOLUTE(.);
. = . + HEAP_SYS_RUNTIME_T_SIZE;
_system_runtime_heap_end = ABSOLUTE(.);
} >system_runtime_heap :system_runtime_heap_phdr

.runtime_heap (NOLOAD) : ALIGN(8)
{
. = ALIGN (32);
_runtime_heap_start = ABSOLUTE(.);
. = . + HEAP_RUNTIME_SIZE;
_runtime_heap_end = ABSOLUTE(.);
} >runtime_heap :runtime_heap_phdr

.buffer_heap (NOLOAD) : ALIGN(8)
{
. = ALIGN (32);
_buffer_heap_start = ABSOLUTE(.);
. = . + HEAP_BUFFER_SIZE;
_buffer_heap_end = ABSOLUTE(.);
} >buffer_heap :buffer_heap_phdr

.sof_stack (NOLOAD) : ALIGN(8)
{
. = ALIGN (4096);
_sof_stack_start = ABSOLUTE(.);
. = . + SOF_STACK_TOTAL_SIZE;
_sof_stack_end = ABSOLUTE(.);
} >sof_stack :sof_stack_phdr

.static_log_entries (COPY) : ALIGN(1024)
{
*(*.static_log*)
Expand Down
8 changes: 4 additions & 4 deletions src/platform/apollolake/boot_ldr.x.in
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Original file line number Diff line number Diff line change
Expand Up @@ -28,11 +28,11 @@ MEMORY
org = IMR_BOOT_LDR_DATA_BASE,
len = IMR_BOOT_LDR_DATA_SIZE
sof_bss_data :
org = IMR_BOOT_LDR_BSS_BASE,
org = IMR_BOOT_LDR_BSS_BASE,
len = IMR_BOOT_LDR_BSS_SIZE
sof_stack :
org = SOF_STACK_END,
len = SOF_STACK_BASE - SOF_STACK_END
org = BOOT_LDR_STACK_BASE,
len = BOOT_LDR_STACK_SIZE
wnd0 :
org = HP_SRAM_WIN0_BASE,
len = HP_SRAM_WIN0_SIZE
Expand Down Expand Up @@ -180,7 +180,7 @@ SECTIONS
_memmap_cacheattr_wbna_trapnull = 0xFF42FFF2;
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull);

__stack = SOF_STACK_BASE;
__stack = BOOT_LDR_STACK_BASE + BOOT_LDR_STACK_SIZE;
__wnd0 = HP_SRAM_WIN0_BASE;
__wnd0_size = HP_SRAM_WIN0_SIZE;

Expand Down
84 changes: 51 additions & 33 deletions src/platform/apollolake/include/platform/memory.h
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Expand Up @@ -152,17 +152,12 @@
(HEAP_SYS_RUNTIME_M_SIZE + ((PLATFORM_CORE_COUNT - 1) * \
HEAP_SYS_RUNTIME_S_SIZE))

#define HEAP_RUNTIME_BASE \
(HEAP_SYS_RUNTIME_0_BASE + HEAP_SYS_RUNTIME_M_SIZE + \
((PLATFORM_CORE_COUNT - 1) * HEAP_SYS_RUNTIME_S_SIZE))

#define HEAP_RUNTIME_SIZE \
(HEAP_RT_COUNT64 * 64 + HEAP_RT_COUNT128 * 128 + \
HEAP_RT_COUNT256 * 256 + HEAP_RT_COUNT512 * 512 + \
HEAP_RT_COUNT1024 * 1024)

#define HEAP_BUFFER_BASE (HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE)
#define HEAP_BUFFER_SIZE (SOF_STACK_END - HEAP_BUFFER_BASE)
#define HEAP_BUFFER_SIZE 0x2000
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#define HEAP_BUFFER_BLOCK_SIZE 0x180
#define HEAP_BUFFER_COUNT (HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE)

Expand All @@ -172,24 +167,44 @@
/*
* The HP SRAM Region Apollolake is organised like this :-
* +--------------------------------------------------------------------------+
* | Offset | Region | Size |
* +---------------------+----------------+-----------------------------------+
* | HP_SRAM_BASE | DMA | HEAP_HP_BUFFER_SIZE |
* +---------------------+----------------+-----------------------------------+
* | SRAM_TRACE_BASE | Trace Buffer W3| SRAM_TRACE_SIZE |
* +---------------------+----------------+-----------------------------------+
* | SRAM_DEBUG_BASE | Debug data W2 | SRAM_DEBUG_SIZE |
* +---------------------+----------------+-----------------------------------+
* | SRAM_EXCEPT_BASE | Debug data W2 | SRAM_EXCEPT_SIZE |
* +---------------------+----------------+-----------------------------------+
* | SRAM_STREAM_BASE | Stream data W2 | SRAM_STREAM_SIZE |
* +---------------------+----------------+-----------------------------------+
* | SRAM_INBOX_BASE | Inbox W1 | SRAM_INBOX_SIZE |
* +---------------------+----------------+-----------------------------------+
* | SRAM_SW_REG_BASE | SW Registers W0| SRAM_SW_REG_SIZE |
* +---------------------+----------------+-----------------------------------+
* | SRAM_OUTBOX_BASE | Outbox W0 | SRAM_MAILBOX_SIZE |
* +---------------------+----------------+-----------------------------------+
* | Offset | Region | Size |
* +------------------+-------------------------+-----------------------------+
* | HP_SRAM_BASE | DMA | HEAP_HP_BUFFER_SIZE |
* +------------------+-------------------------+-----------------------------+
* | SRAM_SW_REG_BASE | SW Registers W0 | SRAM_SW_REG_SIZE |
* +------------------+-------------------------+-----------------------------+
* | SRAM_OUTBOX_BASE | Outbox W0 | SRAM_MAILBOX_SIZE |
* +------------------+-------------------------+-----------------------------+
* | SRAM_INBOX_BASE | Inbox W1 | SRAM_INBOX_SIZE |
* +------------------+-------------------------+-----------------------------+
* | SRAM_DEBUG_BASE | Debug data W2 | SRAM_DEBUG_SIZE |
* +------------------+-------------------------+-----------------------------+
* | SRAM_EXCEPT_BASE | Debug data W2 | SRAM_EXCEPT_SIZE |
* +------------------+-------------------------+-----------------------------+
* | SRAM_STREAM_BASE | Stream data W2 | SRAM_STREAM_SIZE |
* +------------------+-------------------------+-----------------------------+
* | SRAM_TRACE_BASE | Trace Buffer W3 | SRAM_TRACE_SIZE |
* +------------------+-------------------------+-----------------------------+
* | SOF_FW_START | text | |
* | | data | |
* | | ----------------------- | |
* | ||BSS: || |
* | ||-----------------------++-----------------------------+
* | ||Runtime Heap || HEAP_RUNTIME_SIZE |
* | ||-----------------------++-----------------------------+
* | ||Module Buffers || HEAP_BUFFER_SIZE |
* | ||-----------------------++-----------------------------+
* | ||Master core Sys Heap || HEAP_SYSTEM_M_SIZE |
* | ||-----------------------++-----------------------------+
* | ||Master Sys Runtime Heap|| HEAP_SYS_RUNTIME_M_SIZE |
* | ||-----------------------++-----------------------------+
* | ||Master core Stack || SOF_STACK_SIZE |
* | ||-----------------------++-----------------------------+
* | ||Slave core Sys Heap || SOF_CORE_S_T_SIZE |
* | ||Slave Sys Runtime Heap || |
* | ||Slave core Stack || |
* | | ----------------------- | |
* +------------------+-------------------------+-----------------------------+
*/

/* HP SRAM */
Expand Down Expand Up @@ -268,9 +283,6 @@
#define SOF_FW_START (HP_SRAM_VECBASE_RESET + 0x400)
#define SOF_FW_BASE (SOF_FW_START)

/* max size for all var-size sections (text/rodata/bss) */
#define SOF_FW_MAX_SIZE (0x41000 - 0x400)

/* Skylake or kabylake HP-SRAM config */
#elif defined(CONFIG_KABYLAKE) || defined(CONFIG_SKYLAKE)

Expand All @@ -286,23 +298,25 @@
#define SOF_FW_START HP_SRAM_VECBASE_RESET
#define SOF_FW_BASE (SOF_FW_START + 0x1000)

/* max size for all var-size sections (text/rodata/bss) */
#define SOF_FW_MAX_SIZE 0x40000

#else
#error Platform not specified
#endif

/* max size for all var-size sections (text/rodata/bss) */
#define SOF_FW_MAX_SIZE (HP_SRAM_BASE + HP_SRAM_SIZE - SOF_FW_BASE)

#define SOF_TEXT_START (SOF_FW_START)
#define SOF_TEXT_BASE (SOF_FW_START)

/* Stack configuration */
#define SOF_STACK_SIZE ARCH_STACK_SIZE
#define SOF_STACK_TOTAL_SIZE ARCH_STACK_TOTAL_SIZE
#define SOF_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE)
#define SOF_STACK_END (SOF_STACK_BASE - SOF_STACK_TOTAL_SIZE)

#define SOF_MEMORY_SIZE (SOF_STACK_BASE - HP_SRAM_BASE)
/* SOF Core S configuration */
#define SOF_CORE_S_SIZE \
ALIGN((HEAP_SYSTEM_S_SIZE + HEAP_SYS_RUNTIME_S_SIZE + SOF_STACK_SIZE),\
SRAM_BANK_SIZE)
#define SOF_CORE_S_T_SIZE ((PLATFORM_CORE_COUNT - 1) * SOF_CORE_S_SIZE)

/*
* The LP SRAM Heap and Stack on Apollolake are organised like this :-
Expand Down Expand Up @@ -414,6 +428,10 @@
#define IMR_BOOT_LDR_BSS_BASE 0xB0100000
#define IMR_BOOT_LDR_BSS_SIZE 0x10000

/* Temporary stack place for boot_ldr */
#define BOOT_LDR_STACK_BASE HEAP_HP_BUFFER_BASE
#define BOOT_LDR_STACK_SIZE SOF_STACK_TOTAL_SIZE

/** \brief Manifest base address in IMR - used by boot loader copy procedure. */
#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0004000

Expand Down
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