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ASoC: SOF: Intel: BYT: correct shim register reading - #1489
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@plbossart This is good to merge? |
no, the fixes tag is wrong Fixes: 9e42c5c ("ASoC: SOF: Intel: Add BYT, CHT and BSW DSP HW support") |
It is already like that? |
I gave you the correct tag last week already. 3a9e204 (Liam Girdwood 2019-09-27 15:05:37 -0500 148) u32 st |
Oh shoot, my bad, didn't get your exact point during several ping-pong conservations. |
The shim registers in BYT/CHT/BSW are 64bits based, correct the copy/paste (from bdw.c where the shim registers are 32bits based) error in byt_dump(). Fixes: 3a9e204 ("ASoC: SOF: Intel: Add context data to any IPC timeout") Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
The shim registers in BYT/CHT/BSW are 64bits based, correct the wrong
32bits used in byt_dump().
Signed-off-by: Keyon Jie yang.jie@linux.intel.com