Atomic operations on potentially uninitialized integers.
Copying types containing uninitialized bytes (e.g., padding), via the standard library's atomic types is undefined behavior because the copy goes through integers.
This crate provides a way to soundly perform such operations.
Currently, all CPU architectures supported by Rust (x86, x86_64, Arm, AArch64, Arm64EC, RISC-V, LoongArch, s390x, PowerPC, MIPS, SPARC, AVR, MSP430, Hexagon, M68k, C-SKY, and Xtensa) and BPF are supported.
(You can use cfg_{has,no}_* macros to write code based on which primitive sizes are available for the current target and Rust version.)
| target_arch | primitives | load/store | swap/CAS |
|---|---|---|---|
| x86 | isize,usize,i8,u8,i16,u16,i32,u32,i64,u64 | ✓ | ✓ |
| x86_64 | isize,usize,i8,u8,i16,u16,i32,u32,i64,u64 | ✓ | ✓ |
| x86_64 (+cmpxchg16b) [2] | i128,u128 | ✓ | ✓ |
| arm (v6+ or Linux/Android) | isize,usize,i8,u8,i16,u16,i32,u32 | ✓ | ✓[1] |
| arm (except for M-profile) [3] | i64,u64 | ✓ | ✓ |
| aarch64 | isize,usize,i8,u8,i16,u16,i32,u32,i64,u64,i128,u128 | ✓ | ✓ |
| arm64ec [10] | isize,usize,i8,u8,i16,u16,i32,u32,i64,u64,i128,u128 | ✓ | ✓ |
| riscv32 | isize,usize,i8,u8,i16,u16,i32,u32 | ✓ | ✓[1] |
| riscv32 (+zacas) [4] | i64,u64 | ✓ | ✓ |
| riscv64 | isize,usize,i8,u8,i16,u16,i32,u32,i64,u64 | ✓ | ✓[1] |
| riscv64 (+zacas) [4] | i128,u128 | ✓ | ✓ |
| loongarch64 | isize,usize,i8,u8,i16,u16,i32,u32,i64,u64 | ✓ | ✓ |
| loongarch64 (+scq) [5] | i128,u128 | ✓ | ✓ |
| loongarch32 [11] | isize,usize,i8,u8,i16,u16,i32,u32 | ✓ | ✓ |
| s390x [10] | isize,usize,i8,u8,i16,u16,i32,u32,i64,u64,i128,u128 | ✓ | ✓ |
| powerpc [12] | isize,usize,i8,u8,i16,u16,i32,u32 | ✓ | ✓ |
| powerpc64 [12] | isize,usize,i8,u8,i16,u16,i32,u32,i64,u64 | ✓ | ✓ |
| powerpc64 (+quadword-atomics) [6] [12] | i128,u128 | ✓ | ✓ |
| mips / mips32r6 (experimental [13]) | isize,usize,i8,u8,i16,u16,i32,u32 | ✓ | ✓ |
| mips64 / mips64r6 (experimental [13]) | isize,usize,i8,u8,i16,u16,i32,u32,i64,u64 | ✓ | ✓ |
| sparc (experimental [13]) | isize,usize,i8,u8,i16,u16,i32,u32 | ✓ | ✓[1] |
| sparc (+v8plus) [7] (experimental [13]) | i64,u64 | ✓ | ✓ |
| sparc64 (experimental [13]) | isize,usize,i8,u8,i16,u16,i32,u32,i64,u64 | ✓ | ✓ |
| avr (experimental [13]) | isize,usize,i8,u8,i16,u16 | ✓ | ✓ |
| msp430 (experimental [13]) | isize,usize,i8,u8,i16,u16 | ✓ | ✓ |
| hexagon (experimental [13]) | isize,usize,i8,u8,i16,u16,i32,u32,i64,u64 | ✓ | ✓ |
| m68k (experimental [13]) | isize,usize,i8,u8,i16,u16,i32,u32 | ✓ | ✓[1] |
| m68k (+isa-68020) [8] (experimental [13]) | i64,u64 | ✓ | ✓ |
| csky (experimental [13]) | isize,usize,i8,u8,i16,u16,i32,u32 | ✓ | ✓[1] |
| xtensa (experimental [13]) | isize,usize,i8,u8,i16,u16,i32,u32 | ✓ | ✓[1] |
| bpf (+alu32) [9] (experimental [13]) | isize,usize,i32,u32,i64,u64 | ✓ | ✓ |
[1] Arm's RMW operations are not available on Armv6-M (thumbv6m). RISC-V's RMW operations are not available on targets without the A (or G which means IMAFD) or Zalrsc or Zacas extension, such as riscv32i, riscv32imc, etc. 32-bit SPARC's RMW operations requires v9 or leoncasa target feature (enabled by default on Linux). M68k's atomic RMW operations requires target-cpu M68020+ (enabled by default on Linux). C-SKY's atomic RMW operations requires target-cpu ck860* or c860* (enabled by default on the hard-float target). Xtensa's atomic RMW operations are not available on esp32s2.
[2] Requires cmpxchg16b target feature (enabled by default on Apple, Windows (except Windows 7), and Fuchsia targets).
[3] Armv6+ or Linux/Android, except for M-profile architecture such as thumbv6m, thumbv7m, etc.
[4] Requires zacas target feature.
[5] Requires scq target feature and Rust 1.97+.
[6] Requires quadword-atomics target feature (enabled by default on powerpc64le).
[7] Requires v9 and v8plus target features (both enabled by default on Linux).
[8] Requires target-cpu M68020 (Linux's default), M68030, M68040, or M68060 (Linux/NetBSD only).
[9] Requires alu32 target feature.
[10] Requires Rust 1.84+.
[11] Requires Rust 1.91+.
[12] Requires Rust 1.95+.
[13] Requires nightly due to #![feature(asm_experimental_arch)].
See also Atomic operation overview by architecture for more information about atomic operations in these architectures.
Feel free to submit an issue if your target is not supported yet.
This crate uses inline assembly to implement atomic operations (this is currently the only sound way to perform atomic operations on uninitialized values), so it is currently not compatible with Miri and most kinds of Sanitizers.
- portable-atomic: Portable atomic types including support for 128-bit atomics, atomic float, etc.
- atomic-memcpy: Byte-wise atomic memcpy.
- asmtest: A library for tracking generated assemblies.
Licensed under either of Apache License, Version 2.0 or MIT license at your option.
Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.