[heiher]

Tracking issue: rust-lang/rust#162508

LoongArch64 SIMD intrinsics are already used by rustc itself and by a number of downstream projects. Experience from these real-world uses indicates that the API is ready for stabilization. Stabilizing the intrinsics would remove the nightly requirement for applications that currently depend on them.

API surface

• core::arch::loongarch64::lsx_*
• core::arch::loongarch64::lasx_*

Note for subtree update

Remove this line: https://github.com/rust-lang/rust/blob/1edd55dcfcd573872c727fa3e086369a71661ee0/compiler/rustc_span/src/lib.rs#L20

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[tgross35]

Note that this stabilizes more cases of rustc_legacy_const_generics, which was discussed at rust-lang/rust#149654. Cc @rust-lang/lang

Nominating since that's probably worth clarifying, and also this is a lot of surface area with potential sharp edges.

@rustbot label +I-libs-nominated

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[heiher]

Note that this stabilizes more cases of rustc_legacy_const_generics, which was discussed at rust-lang/rust#149654.

Thanks for pointing this out. As far as I know, no projects currently depend on the LoongArch SIMD API signatures using the rustc_legacy_const_generics form, so there are no legacy compatibility concerns here. If adding new instances of rustc_legacy_const_generics is not desirable, we can simply remove it.

[heiher]

rustc_legacy_const_generics has been removed from LoongArch64 SIMD in v2.

[clarfonthey]

@rfcbot merge libs

[rust-rfcbot]

@clarfonthey has proposed to merge this. The next step is review by the rest of the tagged team members:

• @Amanieu
• @BurntSushi
• @cuviper
• @dtolnay
• @joshtriplett
• @the8472
• @thomcc

No concerns currently listed.

Once a majority of reviewers approve (and at most 2 approvals are outstanding), this will enter its final comment period. If you spot a major issue that hasn't been raised at any point in this process, please speak up!

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[Amanieu]

It would be nice to have this fuzz tested against the C intrinsics using intrinsic-test before stabilizing.

@rfcbot concern fuzz testing

[adamgemmell]

There was a previous attempt at doing so at #1900, though it never fully passed CI and will need some rebasing.

[heiher]

There was a previous attempt at doing so at #1900, though it never fully passed CI and will need some rebasing.

Thanks! There's a new impl in #2226 with all related CI checks passing.

[traviscross]

With these intrinsics, Miri reports UB in safe code:

#![feature(stdarch_loongarch)]
use std::arch::is_loongarch_feature_detected;
use std::arch::loongarch64::*;

#[target_feature(enable = "lsx")]
fn probe() -> i32 {
  let ones = lsx_vrepli_b::<1>();
  let zero = lsx_vrepli_b::<0>();
  let r = lsx_vdiv_b(ones, zero);
  lsx_vpickve2gr_b::<0>(r)
}

fn main() {
  if is_loongarch_feature_detected!("lsx") {
    // SAFETY: We just checked: the `lsx` feature is present.
    let lane0 = unsafe { probe() };
    println!("lane 0 = {lane0}");
  }
}

Godbolt link

From #2078, see:

• https://triagebot.infra.rust-lang.org/gh-comments/rust-lang/stdarch/pull/2078#discussion_r3121430126
• https://triagebot.infra.rust-lang.org/gh-comments/rust-lang/stdarch/pull/2078#discussion_r3121435644
• https://triagebot.infra.rust-lang.org/gh-comments/rust-lang/stdarch/pull/2078#discussion_r3121452899

cc @sayantn

[heiher]

With these intrinsics, Miri reports UB in safe code:

Good catch!

I double-checked this with the LoongArch ISA developer. It differs from the previous comment in PR #2078. The ISA defines vdiv/vmod to return 0 if the divisor is 0. (This behavior will be documented in the SIMD reference)

So it seems we can't use portable simd_div/simd_rem here. I'll revert this part. Any other better approach? Thanks!

[Amanieu]

There are 2 options, depending on what the intrinsic behavior should be:

1. Make it unsafe and declare that it is UB if any vector lane of the divisor is 0.
2. Keep it safe and use LLVM target-specific intrinsics or inline asm to implement it.

[heiher]

There are 2 options, depending on what the intrinsic behavior should be:

1. Make it unsafe and declare that it is UB if any vector lane of the divisor is 0.
2. Keep it safe and use LLVM target-specific intrinsics or inline asm to implement it.

Thanks! A new PR has been created based on option 2: #2229

[rustbot]

This PR was rebased onto a different main commit. Here's a range-diff highlighting what actually changed.

Rebasing is a normal part of keeping PRs up to date, so no action is needed—this note is just to help reviewers.

[rust-rfcbot]

🔔 This is now entering its final comment period, as per the review above. 🔔

[rust-rfcbot]

The final comment period, with a disposition to merge, as per the review above, is now complete.

As the automated representative of the governance process, I would like to thank the author for their work and everyone else who contributed.

[heiher]

a gentle ping.

[tgross35]

Stabilization LGTM so I'll approve this. However, there is no documentation anywhere. Would it be possible to send an update adding links and, if possible, descriptions? Similar to what other arches have.

View changes since this review

[tgross35]

Looks like stdarch needs a sync back

[heiher]

Stabilization LGTM so I'll approve this. However, there is no documentation anywhere. Would it be possible to send an update adding links and, if possible, descriptions? Similar to what other arches have.

Thanks! I'll add links to the official LoongArch reference docs once they become available.