Add RX FIFO overflow detection and status flag in UART

[Anubhav-30]

Adds overflow detection and reporting to UART RX path for improved robustness.

Changes

• Introduced rx_overflow register to track overflow condition
• Detects overflow when RX FIFO is full and new data arrives
• Exposes overflow status via Line Status Register (LSR) bit [1]
• Clears overflow flag when LSR is read

Impact

• Improves UART reliability and debugging capability
• Helps detect data loss due to FIFO overflow
• No impact on existing functionality
• Fully backward compatible

Notes

• Overflow logic implemented in sequential (clocked) block
• Avoids combinational assignment to sequential signals
• Follows standard RTL design practices