Consolidate cfg gate blocks in chipset device construction #3540

During the i440bx host PCI bridge resourcification (#3331), reviewer feedback noted that the growing number of individual #[cfg(guest_arch = "x86_64")] blocks in chipset device construction code could be consolidated into fewer, larger blocks to reduce visual noise and improve readability.

This is a cleanup/refactor task — no behavioral change expected.

Areas to review

• vmm_core/vmotherboard/src/base_chipset.rs — device deps construction
• openvmm/openvmm_core/src/worker/dispatch.rs — device handle emission
• openhcl/underhill_core/src/worker.rs — OpenHCL device construction

Context

As more x86-only devices get resourcified (ISA DMA, CMOS RTC, PIT, PIIX4, i440BX), each adds its own cfg gate. Merging adjacent gates into consolidated blocks would be cleaner.