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Please Help: LVS error on 1024x8bit ROM (new user) #319
Description
Hi,
I've recently discovered the OpenRAM project, thanks much for sharing it!
To acquaint myself with the project and its tooling, I have made a
first-pass attempt at creating a 1024x8bit ROM populated with random
data. Here are the steps I followed (after installing all necessary
prerequisites):
git clone https://github.com/VLSIDA/OpenRAM
cd OpenRAM
nix develop
export OPENRAM_HOME=$(pwd)/compiler
export OPENRAM_TECH=$(pwd)/technology
export PDK_ROOT=$(pwd)
export PYTHONPATH=$OPENRAM_HOME:$PYTHONPATH
make sky130-pdk
make sky130-install
# create (random) 1K hex data file:
for ((i=0; i<1024; i++)); do
let VAL=$RANDOM%256
printf "%02X" $VAL
done > rom_1kbyte.hex
I am using the following content as rom_1kbyte.py:
word_size = 1
check_lvsdrc = True
rom_data = "rom_1kbyte.hex"
data_type = "hex"
tech_name = "sky130"
output_path = "rom_1kbyte"
output_name = "rom_1kbyte"
nominal_corner_only = True
route_supplies = "ring"
keep_temp = TrueI then ran the following build command:
./rom_compiler.py rom_1kbyte.py
and received the following output:
|==============================================================================|
|========= OpenRAM v1.2.49 =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= Computer Science and Engineering Department =========|
|========= University of California Santa Cruz =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= See LICENSE for license info =========|
|==============================================================================|
** Start: 10/07/2026 15:40:28
Output files are:
/home/user/OpenRAM/rom_1kbyte/rom_1kbyte.sp
/home/user/OpenRAM/rom_1kbyte/rom_1kbyte.v
/home/user/OpenRAM/rom_1kbyte/rom_1kbyte.lef
/home/user/OpenRAM/rom_1kbyte/rom_1kbyte.gds
create rom of word size 1 with 1024 num of words
** Submodules: 44.0 seconds
** Placement: 0.0 seconds
** Routing: 77.5 seconds
WARNING: file magic.py: line 254: DRC Errors rom_1kbyte 830
ERROR: file magic.py: line 385: rom_1kbyte LVS mismatch (results in /tmp/openram_user_373924_temp/rom_1kbyte.lvs.report)
** Verification: 929.6 seconds
** ROM creation: 1051.1 seconds
SP: Writing to /home/user/OpenRAM/rom_1kbyte/rom_1kbyte.sp
** Spice writing: 0.3 seconds
GDS: Writing to /home/user/OpenRAM/rom_1kbyte/rom_1kbyte.gds
** GDS: 0.3 seconds
LEF: Writing to /home/user/OpenRAM/rom_1kbyte/rom_1kbyte.lef
** LEF: 0.0 seconds
LVS: Writing to /home/user/OpenRAM/rom_1kbyte/rom_1kbyte.lvs.sp
** LVS writing: 0.3 seconds
Config: Writing to /home/user/OpenRAM/rom_1kbyte/rom_1kbyte.py
** Config: 0.0 seconds
Verilog: Writing to /home/user/OpenRAM/rom_1kbyte/rom_1kbyte.v
** Verilog: 0.0 seconds
[openram.globals/cleanup_paths]: Preserving temp directory: /tmp/openram_user_373924_temp/
** End: 1052.0 seconds
I'm attaching rom_1kbyte.lvs.report.gz (file mentioned in the error message), as well as rom_1kbyte.lvs.out.txt.
Any comments/advice on how serious this error might be, and on just how "broken" my resulting 1K ROM design might be would be much appreciated!
Many thanks in advance!
Activity
mguthaus commentedon Oct 7, 2026
gsomlo commentedon Oct 7, 2026