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Sense amp enable timing error when generating 1 Kb (1024 bits) SRAM — requires manual delay chain adjustment #274
Description
When trying to generate a 1 Kb (1024 bits / 1 KB) SRAM, OpenRAM fails due to a “Sense amp enable timing error.”
I tried manually increasing the delay chain through the configuration file, but this didn't helped.
I used all default options of OpenRAM for sram_32x32(with freepdk45 technology).
ERROR: file delay.py: line 918: Sense amp enable timing error. Increase the delay chain through the configuration file.
Activity
mguthaus commentedon Oct 16, 2025
Increasing the delay chain manually should over-ride the length completely, so you likely didn't pick an appropriate length (or it wasn't done properly). It's possible that there is another issue, but you will need to diagnose further. Sorry, but we don't have much support at this time and will welcome any PR that you might have to fix any issues.
mguthaus commentedon Oct 13, 2026
Still open. Sense amp enable timing comes out of
compiler/modules/control_logic_delay.pyand the replica bitline path, and #276 is a related control-logic timing report on freepdk45 that is also open.One thing worth knowing if you look at this:
control_logic_delay.pycomputes its capacitances asspice["wire_unit_c"] * 1e15, treating the value as F/um^2, whilecompiler/base/wire_spice_model.pyuses* 1e12on the same value. Those cannot both be right, and PR #223 is an open fix for it. For sky130 the stored value is in fF/um^2, so the control-logic numbers are currently off by a large factor.If you would like to take it, a PR against
devwould be very welcome and we will review and consider it — see CONTRIBUTING.md. Contributions go to thedevbranch, and the regression suite is run withcd compiler/tests && make -k -j<N>.