From 0764fb1d459e6c0c14466ac9e4bae6417f9c4123 Mon Sep 17 00:00:00 2001 From: Jyothikala P Date: Thu, 5 Nov 2026 15:32:55 +0530 Subject: [PATCH] platform: amd: acp_7_x: re-enable S5 refclk for the DSP external timer The Zephyr AMD_ACP_TIMER driver uses the ACP DSP0 External Timer1 as the system tick. This timer counts on S5_REFCLK, which must run at the 24 MHz reference rate. Restore the commented-out acp_s5_refclk_config() call in acp_clk_d0_sequence() so S5_REFCLK is put back on the 24 MHz reference after the DFS divider is programmed. Signed-off-by: Jyothikala P --- src/platform/amd/acp_7_x/lib/clk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/platform/amd/acp_7_x/lib/clk.c b/src/platform/amd/acp_7_x/lib/clk.c index a6eb97642711..578b35bb0ab6 100644 --- a/src/platform/amd/acp_7_x/lib/clk.c +++ b/src/platform/amd/acp_7_x/lib/clk.c @@ -424,7 +424,7 @@ void acp_clk_d0_sequence(uint32_t clock_freq) /* Run ACP off the undivided ACLK enable acp_clkmux_sel(ACP_CLK_DIV_BY_1);*/ /* Only now program the DFS divider: the slice is off bypass */ change_clock_notify(clock_freq); - /* S5_REFCLK back on the 24 MHz reference with the postdiv reset to enable it acp_s5_refclk_config(0, ACP_CLK_BYPASS_SEL_REFCLK_24MHZ, 0);*/ + acp_s5_refclk_config(0, ACP_CLK_BYPASS_SEL_REFCLK_24MHZ, 0); /* restore io clk acp_io_clk_sel_restore();*/ }